1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
In the context of memory devices, such as static random access memory (SRAM), a “soft error” is a non-permanent memory error. Most soft errors may be fixed by simply writing new data to the memory. It is well known that alpha particles can cause soft errors. This phenomenon is further described with reference to FIG. 1.
FIG. 1 shows a schematic diagram of a cross-section of a substrate having a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor. The PMOS and NMOS transistors are formed in an N-well 103 and a P-well 106, respectively. In the example of FIG. 1, the highly doped region labeled as 104 represents P+ doped regions of the PMOS transistor, such as source and drain regions. The P+/N-well junction is labeled as 105. Similarly, the highly doped region labeled as 107 represents N+ doped regions of the NMOS transistor, such as source and drain regions. The N+/P-well junction is labeled as 108. For clarity of illustration, FIG. 1 does not show all the regions and structures of the transistors.
When an alpha particle hits the silicon area of the NMOS transistor, for example, electron-hole pairs are generated along the trajectory of the particle. The generated carriers can be collected by the biased N+/P-well junction 108, thereby flipping the state of the transistor and causing a soft error. Soft errors due to alpha particles become more significant as device geometries shrink. Unfortunately, conventional techniques for dealing with soft errors, such as implementation of well engineering, use of an N+ or P+ buried layer, or use of an epitaxial wafer, are relatively expensive to implement and are not effective enough in some applications.